There are conventional methods of making a capacitor in a semiconductor memory device such as is illustrated in FIG. 1, and also the Spread Vertical Capacitor (SVC) method which discussed in IEDM '91, at pages 473-476.
FIG. 1 illustrates a method of making a capacitor in a semiconductor memory device by a conventional method.
As illustrated in FIG. 1(A), field oxide insulator 11 is formed on silicon substrate 10 and source/drain regions 102 are formed. Thereafter, silicon oxide layer 12 and nitride layer 13 are deposited in the cited order on the overall surface of silicon substrate 10. Contact holes N are formed over and to source/drain regions 102 of silicon substrate 10.
As illustrated in FIG. 1(B), after polysilicon layer 14 to be used as a storage electrode node is deposited in contact holes N1 and N2 and on nitride layer 13, silicon oxide layer 16 and nitride layer 15 are deposited on polysilicon layer 14 in the cited order.
Nitride layer pattern 15 is defined to be used as a mask for etching a portion of silicon oxide layer 16 by a photolithographic process.
As illustrated in FIG. 1(C), silicon oxide layer pattern 16' and polysilicon layer pattern 14' are defined by an anisotropic etching with a mask of nitride layer pattern 15, using nitride layer 13 as an etch-stopping layer.
After nitride layer pattern 15 is removed, polysilicon layer 17 is deposited on the surface and sides of silicon oxide layer 16, the sides of polysilicon layer pattern 14' and on nitride layer 13.
As illustrated in FIG. 1(D), after sidewall spacer 17' is formed around silicon oxide layer pattern 16' by a reactive ion etching of polysilicon layer 17, a cylinder-shaped storage electrode is formed by etching silicon oxide layer pattern 16' in an HF solution.
Dielectric layer 110 is formed on the cylinder-shaped storage electrode, and a capacitor plate electrode (not shown) is formed on dielectric layer 110. The method of making the capacitor thus is completed.
FIG. 2 illustrates a layout of a capacitor which is fabricated in accordance with the method as illustrated in FIG. 1. Rectangle area 21 represents a capacitor area of a cell, N1 and N2 represent contacts. Also shown are bit lines 23 and active area 25.
FIG. 3 illustrates the SVC method of making a capacitor in a semiconductor memory device.
As illustrated in FIG. 3(A), after formation of field insulator 31, circuit elements such as source/drain regions 31-1 and word lines 31-2 are formed on silicon substrate 30, and insulating layer 32 and nitride layer 33 are deposited on silicon substrate 30 in the cited order.
Contact holes 10A, 10B, 10C are formed onto source/drain regions 31-1, and polysilicon layer 34 is deposited on substrate 30. A silicon oxide layer is deposited on polysilicon layer 34 and a trench is formed in the silicon oxide layer, resulting in silicon oxide layer pattern 38.
As illustrated in FIG. 3(B), a polysilicon layer is deposited on the surface, and storage electrode 37 is formed by anisotropic dry etching of the polysilicon layer.
As illustrated in FIG. 3(C), after silicon oxide pattern 38 is removed, sidewall spacer 38' of silicon oxide is formed at the outer side of storage electrode 37 and a polysilicon layer is formed on the surface. Storage electrode 37' is formed by etching anisotropically the polysilicon layer. Storage electrode 37 has nearly the same capacitance as storage electrode 37' on account of a difference in height (the height of electrode 37' is smaller than the height of electrode 37).
As illustrated in FIG. 3(D), after sidewall spacer 38' is removed, storage electrode 37(A') is isolated electrically from storage electrode 37' (B') by anisotropic dry etching of the whole surface of silicon substrate 30. An ONO (dielectric) layer (not shown) and a plate electrode (not shown) are formed on storage electrodes A' and B' in the cited order.
FIG. 4 illustrates a layout of a capacitor which is fabricated in accordance with the SVC method, wherein storage electrode A' is connected to electrode contact 10A, and storage electrode B' which can be made by self-alignment is connected to electrode contact 10B. The dashed lines illustrate active areas.
In conventional methods such as illustrated in FIG. 1 and FIG. 2, it is a problem that the area of a storage electrode, which is a measure of its capacitance, is limited within a single cell, naturally causing difficulties in making ultra-highly integrated memory cells.
The SVC method as illustrated in FIG. 3 and FIG. 4 has a problem of strict alignment margin. In addition, the SVC method has a weak point of an increased resistance generated from the narrow alignment margin as outer wall loop B' in FIG. 4 is connected to a portion of electrode contact 10B, and the capacitance area of storage electrode A' is confined only within the wall of inner loop A'.